Industry Immersion Program in IC Design

1. MBOT-certified micro-credential training on front-end digital IC design by experienced industry experts.

2. Industry-endorsed training focused on the most sought-after IC design skills.

3. Group Capstone Project with dedicated mentorship from an industry expert — 15 hours of guidance included.

4. Prepare academia to immerse in industry-relevant IC design practices.

5. Facilitate sabbatical placement opportunities for academia within leading IC design MNC.

MicroDegree in Digital IC Design: Front-End Design

Synopsis
This comprehensive training programme is designed to equip participants with end-to-end knowledge and practical skills in the field of Integrated Circuit (IC) design and verification. With the rapid growth of the semiconductor industry and increasing demand for high-performance, low-power chips, the programme provides a solid foundation in the design methodologies, tools, and workflows adopted by industry practitioners.

The learning journey begins with a deep dive into the IC design ecosystem, covering key stages from architecture definition to post-silicon validation. Participants will explore digital system design using Verilog HDL and progressively develop their competency in constructing RTL models, pipelined datapaths, and full digital systems. The programme then transitions to modern verification techniques, emphasizing the use of SystemVerilog for both synthesizable design and testbench development.

Advanced verification methodologies are introduced through the Universal Verification Methodology (UVM), empowering learners to build scalable and reusable test environments for complex SoCs. The programme combines conceptual lectures with practical lab work using industry tools. It ensures learners can apply theoretical knowledge directly to real-world design challenges.

What You Will Learn

• The full IC design flow from pre-silicon to post-silicon stages

• RTL design principles using Verilog HDL and best practices for synthesis

• Pipelined datapath construction and optimization techniques

• Hands-on design and verification using EDA tools

• SystemVerilog constructs for advanced RTL modeling and simulation

• Building SystemVerilog testbenches using assertions, interfaces, and classes

• Applying UVM for scalable verification, including agents, sequences, and scoreboards

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RM18,000 PER PAX

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